The present invention generally relates to storage media, and more particularly, the present invention relates to a method and system for recovering data in a nonvolatile memory.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 2006-104152, filed Oct. 25, 2006, the entire contents of which are hereby incorporated by reference.
Flash memories are typically classified as either NOR type or NAND type depending upon the manner in which memory cells are interconnected with bit lines. NOR flash memories are capable of relatively fast read operations, and hence are often utilized for code storage. On the other hand, NAND flash memories are capable of relatively high write frequencies, and are often employed as low-cost, high capacity data storage media.
In both NOR type and NAND type flash memories, each unit memory cell must be in an erased state prior to programming. In addition, erase functions are typically executed in units of erase blocks or erase zones containing large quantities of memory cells. These and other characteristics of flash memory necessitate the use of a “flash translation layer” (FTL) between the flash memory and the file system of the device. FTL generally functions to conceal the erase operations of the flash memory, and to emulate a storage device such as a disc drive or other mass-storage device. For example, during a write operation, the FTL functions to map physical addresses of the flash memory with logical addresses generated by the file system. In order to achieve a fast mapping operation, FTL uses an address mapping table typically composed of static random access memory (RAM). The address mapping function of FTL allows a host to identify flash memory as a hard disk drive (HDD) or static RAM, and to access the flash memory in the same manner as an HDD or static RAM.
As an example of block address mapping by FTL, FIG. 1 is a diagram showing of a virtual block mapping scheme. As shown, “n” logical address domain blocks LBN_0 through LBN_n−1 are mapped to “n+m” physical address domain blocks PBN_0 through PBN_n−1 and RBN_0 through RBN_m−1. The “m” physical address domain blocks in excess of the “n” logical domain blocks may be deemed spare blocks which are utilized in place of abnormal (“bad”) blocks.
Mapping of the logical address domain blocks to the physical address domain blocks is dynamic in the sense that the mapping of the logical address domain blocks to the physical address domain blocks is not fixedly defined. For example, a “wear-leveling” scheme may be adopted to prolong the life of the memory blocks of the flash memory. For example, wear-leveling may include storing information indicative of an erase count for each memory block, and assigning logical block addresses to those memory blocks having the smallest erase counts
In the meantime, upon the occurrence of an inadvertent power loss (e.g., power failure), it is necessary during reboot to recover and restore the FTL mapping information. This is conventionally done by executing a process in which mapping information from a specific field included in each block is read by scanning all blocks, and then restoring a mapping table composed in RAM (random access memory). This process suffers the disadvantage of consuming time and resources during reboot.